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Intel co-founder Gordon Moore famously predicted that the number of transistors on a chip would double every one to two years. This prediction, known as Moore’s Law, held true until recently due to developments in pattern-minimization technology. However, Moore’s Law may no longer be valid as technological progress has reached its limits and costs have increased with the use of expensive equipment such as extreme ultraviolet (EUV) lithography systems. Meanwhile, there is still a great market demand for ever-improving semiconductor technologies. To bridge this gap in technological progress and meet the needs of the semiconductor market, a solution has emerged: Advanced semiconductor packaging technology.
Although advanced packaging is highly complex and involves a wide mix of technologies, Interconnection technology remains at its core. This article will explain how packaging technology has evolved and discuss SK Hynix’s recent efforts and achievements in advancing the field.
Importance of Interconnection in Advanced Packaging
First, it is important to note that interconnection technology is an important and necessary part of packaging. The chips are interconnected through packaging to receive power, exchange signals, and ultimately operate. Because the speed, density, and function of a semiconductor product depend on how the interconnections are made, interconnection methods are constantly changing and evolving.
In addition to developing various processes for realizing fine patterns in the FAB, extensive efforts have been made to advance interconnection techniques in the packaging process. As a result, the following four types of interconnection technology have been developed: wire bonding, flip-chip bonding, through-silicon through1 (TSV) bonding, and hybrid bonding with chiplets.2
1Through-Silicon Via (TSV): A type of vertical interconnect access (through) that passes completely through a silicon die or wafer to enable stacking of silicon dies.
2Chiplet: Technology that splits chips for use such as controllers or high-speed memory and forms them as individual wafers before reassembling them in the packaging process.
3 Hybrid bonding is not implemented on the above products. Specifications are an estimate.
Wire bonding was the first interconnection method that was developed. Typically, materials with good electrical properties such as gold, silver, and copper are used as wires to connect chips and substrates. It is the most cost-effective and reliable interconnection method, but because of its long electrical path, it is not suitable for new equipment that requires high-speed operation. As a result, this method is being adopted for mobile DRAM and NAND chips used in mobile devices that do not require fast operation.
flip-chip bonding Overcomes the drawbacks of wire bonding. Its electrical path length is several tenths of the length found in wire bonding, making it suitable for high speed operation. Processed at the wafer level, flip-chip bonding also provides improved productivity compared to wire bonding performed at the chip level. As a result, it is widely used in the packaging of CPUs, GPUs, and high-speed DRAM chips. In addition, since the leads can be formed along the entire edge of the chip, it is possible to have more inputs and outputs (I/O) than with wire bonding – potentially providing higher data-processing speeds. However, flip-chip bonding has its disadvantages. First, multi-chip stacking is difficult, which is detrimental to memory products that require high density. Furthermore, even though flip-chip bonding can connect more I/Os than wire bonding, its bump pitch3 And the organic PCB pitch prevents the connection of even more I/Os. To overcome these limitations, TSV bonding was developed.
Through-Silicon Via (TSV) Bonding
Instead of using the traditional method of wiring to connect chip-to-chip, TSVs connect chips vertically by drilling holes in the chip and filling them with a conductive material such as metal to accommodate the electrodes., After fabrication of the wafer with TSV, microbumps are made on its top and bottom edges through the packaging before these bumps are added. Since the TSV allows the bumps to be connected vertically, it enables multi-chip stacks. Initially, the stack using TSV bonding had four layers, before this was increased to eight. Recently, a technology made it possible to stack 12 layers, and in April 2023 SK hynix develops its 12-layer HBM3, While the method of flip-chip bonding with TSVs typically uses thermocompression-based non-conductive film (TC-NCF), SK Hynix uses MR-MUF.4 process, which can reduce pressure from stacking and enable self-alignment.5 These features made it possible for SK hynix to develop the world’s first 12-layer HBM3.
4Mass Reflow Molded Underfill (MR-MUF): A process in which semiconductor chips are stacked and a liquid protective material is injected into the space between the chips and then hardened to protect the chips and surrounding circuitry Is. Compared to applying film-type materials after each chip is stacked, MR-MUF is a more efficient process and provides effective heat dissipation.
5Self-alignment: Moving the die to its proper position through mass reflow during the MR-MUF process. During this process heat is applied to the chips, causing the corresponding protrusions to melt and harden into the correct position.
As mentioned above, wire, flip-chip and TSV bonding serve their respective purposes in different areas of the packaging process. Nevertheless, there is a new interconnection technology that has emerged recently called copper-to-copper direct bonding, which is a type of hybrid bonding.
Hybrid Bonding with Chiplets
The term “hybrid” is used to denote this two types of interfacial bonding6 being made together. There are two types of interfacial bonding: bonding between oxide interfaces and bonding between coppers. This technology is not a new development but has been used in mass production of CMOS image sensors for many years. However, it has gained more attention recently due to the increasing use of chipotle. Chiplet technology separates individual chips based on function and then re-combines them through packaging to implement a variety of functions on a single chip.
6Interfacial Bonding: Bonding in which the surfaces of two bodies in contact with each other are held together by intermolecular forces.
Although the functionality of chiplets is a clear advantage of the technology, the primary reason for adopting them is cost-effectiveness. When all functions are implemented on a single chip, the chip size increases and inevitably leads to a loss in yield during wafer production. Additionally, while some areas of the chip may require expensive and complex technology, other areas can be accomplished with inexpensive legacy technology. Thus, the manufacturing process becomes expensive because the chip cannot be isolated, so the finned technology is applied to the entire chip, even if only a small area is needed. However, chiplet technology’s ability to separate chip functions enables the use of advanced or legacy manufacturing techniques and, thus, leads to cost savings.
Although the concept of chiplet technology has been around for more than a decade, it has not been widely adopted due to the lack of development of packaging technology that interconnects the chips. However, recent advances in chip-to-wafer (C2W) hybrid bonding have greatly accelerated the adoption of chiplet technology. C2W hybrid bonding offers several benefits. First, it allows for solder-free bonding which reduces the thickness of the bonding layer, shortens the electrical path, and lowers resistance. Therefore, chiplets can operate at higher speeds without compromise – as if it were a single chip. Second, by connecting copper directly to copper, the pitch at the bumps can be reduced dramatically. Currently, bump pitches of 10 micrometers (μm) or less are difficult to achieve when using solder. However, copper-to-copper direct bonding can reduce the pitch to less than μm, increasing the flexibility in chip design. Third, it provides improved thermal dissipation, a packaging feature whose importance will continue to grow in the future. Finally, the thinner bonding layer and finer pitch mentioned above affect the form factor of the packaging, so the size of the packaging can be reduced dramatically.
However, like other bonding techniques, hybrid bonding still has challenges to overcome. To ensure robust quality, particle control at the nanometer scale must be improved, and controlling the flatness of the bonding layer remains a major obstacle. Meanwhile, SK Hynix plans to use the most high-strength packaging solution to develop hybrid bonding so that it can be applied to future HBM products, such as its 16-layer HBM which is under development.
SK Hynix Advancing Packaging Technology with Hybrid Bonding
While SK hynix is currently developing hybrid bonding for implementation on its upcoming high-density, high-stack HBM product, the company plans to test hybrid bonding for the HBM2E in 2022 by first completing electrical tests and ensuring basic reliability. managed to stack eight layers together. This was an important achievement because most cases of hybrid bonding to date have been done through single-layer bonding, or stacking two chips face-to-face. For the HBM2E, SK hynix successfully stacked one base die and eight DRAM dies.
Hybrid bonding is the most discussed and highlighted bonding technique in the packaging industry. Integrated device manufacturers, foundries and any company capable of producing advanced packages are focusing on hybrid bonding. As mentioned above, the technology still has a long way to go despite its many advantages. through its leadership HBM Technology will develop various packaging technologies in addition to hybrid bonding to help SK Hynix packaging technologies and platform solutions reach unprecedented levels.